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[Other resource] lattice

Description: Lattice 公 司 把 当 今 两 种 最 新 的 系 统 设 计 技 术，VHDL 和 在 系 统 可 编 程 ( ISP ) 逻 辑 器 件 联 系 在 一 起， 构 成 了isp-VHDl Viewlogic 系 统。isp-VHDL 是 进 行 电 子 系 统 设 计 的 强 有 力 的 工 具， 使 用 它 可 以 加 快 设 计 产 品 投 放 市 场 的 时 间。 isp-VHDL Viewlogic 软 件 能 用 于 各 种 逻 辑 设 计， 这 套 软 件 具 有 功 能 强 大 的 VHDL 综 合、原 理 图 输 入、功 能 与 时 序 仿 真、ispDS+ 适 配 器 和 ispDOWNLOAD 能 力。-two companies today the latest design technology, VHDL and in-system programmable (ISP) logic device linked constitute a isp - VHDl Viewlogic Systems. Isp-VHDL is an electronic system designed powerful tool, It can be used to speed up the design of products on the market in time. Isp-VHDL Viewlogic software can be used for various logic design, This software has powerful VHDL synthesis, diagram entry, functional and timing simulation, ispDS adapter and ispDOWNLOAD capacity.
Platform: | Size: 507865 | Author: kurt | Hits:

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

Description: lattice sdram 控制器VHDL源代码-Sound code of Lattice Sdram Controller based on VHDL
Platform: | Size: 180224 | Author: 刘汉忠 | Hits:

[VHDL-FPGA-Verilog] uart_vhdl_lattice

Description: lattice的串口仿真的程序- serial port simulated programme of lattice
Platform: | Size: 43008 | Author: 赵兴涛 | Hits:

[VHDL-FPGA-Verilog] vhdl_LED

Description: 点阵显示实验示例使用说明 使用模块有：时钟源模块、点阵显示模块，脉冲沿模块。 使用步骤： 1. 打开电源+5V。 2. 信号连接，按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线，并将程序加载 4. 脉冲沿模块的按键MS1为复位清零键，灯灭时有效，点阵块上会显示汉字。 -lattice experimental use of the use of sample modules : clock source modules, dot-matrix display module, pulse along the module. Use steps : 1. Turn the power 5V. 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connecting lines and procedures for loading 4. Pulse module along the MS1 to reset button, reset button, when the lights were effective, Lattice pieces will be shown on Chinese characters.
Platform: | Size: 333824 | Author: 刘浪 | Hits:

[Other] lattice

Description: Lattice 公 司 把 当 今 两 种 最 新 的 系 统 设 计 技 术，VHDL 和 在 系 统 可 编 程 ( ISP ) 逻 辑 器 件 联 系 在 一 起， 构 成 了isp-VHDl Viewlogic 系 统。isp-VHDL 是 进 行 电 子 系 统 设 计 的 强 有 力 的 工 具， 使 用 它 可 以 加 快 设 计 产 品 投 放 市 场 的 时 间。 isp-VHDL Viewlogic 软 件 能 用 于 各 种 逻 辑 设 计， 这 套 软 件 具 有 功 能 强 大 的 VHDL 综 合、原 理 图 输 入、功 能 与 时 序 仿 真、ispDS+ 适 配 器 和 ispDOWNLOAD 能 力。-two companies today the latest design technology, VHDL and in-system programmable (ISP) logic device linked constitute a isp- VHDl Viewlogic Systems. Isp-VHDL is an electronic system designed powerful tool, It can be used to speed up the design of products on the market in time. Isp-VHDL Viewlogic software can be used for various logic design, This software has powerful VHDL synthesis, diagram entry, functional and timing simulation, ispDS adapter and ispDOWNLOAD capacity.
Platform: | Size: 507904 | Author: kurt | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[Other] lattice_sdram_source_code

Description: lattice sdram 控制器的源码，VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
Platform: | Size: 31744 | Author: dido wang | Hits:

[VHDL-FPGA-Verilog] uart_vhdl_lattice

Description: UART的rs232通信接口VHDL语言，里面有详细的介绍-UART communication interface rs232 VHDL language, which is described in detail
Platform: | Size: 108544 | Author: 拉拉 | Hits:

[Communication] vc++toled

Description: 本人用在公司点阵条屏通讯送点阵数据的上位几软件,有两点可以参考 1.里面的点阵获取没有采用字库,而是自己从屏幕获取.可以发送WINDOWS有的任意可以写出来的字体. 2.实现了串口的发送.-I used the company lattice screen data communications sent to the upper lattice several software two of which may be a reference. there is no access to the lattice using font, but their access to the screens. Windows can send some arbitrary able to write the characters. 2. achieved a string Send the mouth.
Platform: | Size: 48128 | Author: zxf | Hits:

[VHDL-FPGA-Verilog] dianzheng6.2banben

Description: 8*8点阵的实现，循环显示vhdl四个字母-8* 8 lattice the realization cycle shows vhdl four letters
Platform: | Size: 267264 | Author: jerry | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[VHDL-FPGA-Verilog] trafic

Description: CPLD lattice1032 VHDL实现交通灯控制！-CPLD lattice1032 VHDL to achieve control of traffic lights!
Platform: | Size: 144384 | Author: 徐家汇 | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[Software Engineering] led

Description: 本文主要介绍了 基于FPGA点阵开发的相关内容，对于FPGA开发人员来说是一篇比较不错的文章。-This paper introduces lattice based on the development of FPGA-related content, for FPGA developers is a relatively good article.
Platform: | Size: 133120 | Author: 李明 | Hits:

[MPI] vhd_divider

Description: lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器-lattice isplever7 Treasury did not divide, so the Internet to find a foreigner to write the VHDL divider
Platform: | Size: 6144 | Author: guyh | Hits:

[VHDL-FPGA-Verilog] lattice

Description: 本程序是用VHDL编写，用于实现点阵显示功能。-This procedure is used VHDL to prepare for the realization of dot-matrix display.
Platform: | Size: 135168 | Author: lesslie | Hits:

[VHDL-FPGA-Verilog] Lattice-Machxo-FPGA-Loader

Description: Application note (source code + documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.-Application note (source code+ documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.
Platform: | Size: 664576 | Author: M V | Hits:

[VHDL-FPGA-Verilog] VHDL-FPGA-xilinx-altera-frily

Description: VHDL的经典经验。相当的不错，一个多年开发FPGA的工程师自己的记录，适用于ALTERA,XILINX,LATTICE等FPGA的开发。希望对大家有用。-VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera
Platform: | Size: 3913728 | Author: 何思涵 | Hits:

[VHDL-FPGA-Verilog] matrix

Description: 该源代码是控制16*16点阵的VHDL语言描述，可以让点阵连续显示设置的汉字。-The source code is to control 16* 16 lattice VHDL language description, allowing a continuous dot-matrix display settings of the characters.
Platform: | Size: 909312 | Author: 王伟 | Hits:

[VHDL-FPGA-Verilog] 74HC595-lattice-clock

Description: 74HC595点阵时钟：使用74HC595芯片控制的16*16点阵时钟，流动显示时分秒，单片机：STC12C5A60S2-74HC595 lattice clock: using 74HC595 chip control 16* 16 dot matrix clock, mobile display minutes and seconds, the microcontroller: STC12C5A60S2
Platform: | Size: 30720 | Author: 陈科铭 | Hits:
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